1. Field of the Invention
The present invention generally relates to the field of semiconductor power devices. More particularly, the present invention relates to a method for fabricating a super-junction semiconductor power device with reduced Miller capacitance.
2. Description of the Prior Art
A power device is used in power management; for example, in a switching power supply, a management integrated circuit in the core or peripheral region of a computer, a backlight power supply, and in an electric motor control. The type of power devices described above include an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), and a bipolar junction transistor (BJT), among which the MOSFET is the most widely applied because of its energy saving properties and ability to provide faster switching speeds.
In one kind of power MOSFET device, a P-type epitaxial layer and an N-type epitaxial layer are alternatively disposed to form several PN junctions inside a body and the junctions are vertical to a surface of the body. The device with the described PN junctions is also called a super-junction power MOSFET device. A gate structure is disposed at a cell region of the device to control the on-off state of current. In a conventional super-junction power device, there are some disadvantages to be conquered. For example, a channel length is not easily controlled, which causes the fluctuation of a threshold voltage. A super-junction power MOSFET of the prior art usually has a relatively high Miller capacitance so switching loss is inevitable, and this further reduces the performance of the device.
In light of the above, there is still a need for providing a method for fabricating an improved super-junction power MOSFET which is capable of overcoming the shortcomings and deficiencies of the prior art.